Enterprise NAND

Breakthrough Endurance for Enterprise Storage

Our Enterprise NAND is high-endurance NAND Flash optimized for intensive enterprise storage applications where endurance is the top priority. It far surpasses standard cycle rates and it does it with an industry-standard package, without requiring any design or process changes for existing products.

High-Endurance NAND for Intensive Enterprise Applications

Enterprise NAND is a high-endurance NAND product family optimized for intensive enterprise applications. Breakthrough endurance, coupled with high capacity and high reliability (through low defect and high cycle rates), make Enterprise NAND an ideal storage solution for transaction-intensive data servers and enterprise SSDs.

Our MLC Enterprise NAND offers an endurance rate of 30,000 WRITE/ERASE cycles, or six times the rate of standard MLC, and SLC Enterprise NAND offers 300,000 cycles, or three times the rate of standard SLC. These parts also support the ONFI 2.1 synchronous interface, which improves data transfer rates by four to five times compared to legacy NAND interfaces.

Let us help you get the most out of your enterprise storage application. We’ll leverage the latest processor, controller, and interface designs—and everything we know about NAND—to provide you with the best possible solution.

Enterprise NAND Part Catalog and Documentation

New Breakthroughs for Enterprise NAND

Watch as Micron’s Kevin Kilbuck outlines recent upgrades to our Enterprise NAND product line. You’ll hear about the inherent advantages of designing these parts on our mature 34nm process technology; how our new SLC and MLC Enterprise NAND are able to deliver the highest cycle rates and most capacity of any part on the market; and what these advancements mean for enterprise customers.

About Micron's Innovations Blog
For more videos and forward-looking design discussion, tune into our Innovations Blog. Our blog highlights recent technology developments—from the advanced storage solutions developed by our MAST Center team, to the cutting edge of server, computing, and mobile memory.
View more videos on our Micron Innovations Blog.

NAND Leadership
Micron does more than design and manufacture NAND Flash memory. We strive to solve design challenges through better engineering—by raising the bar on features, functionality, and performance. We’ll work with you so you can leverage our design expertise, systems understanding, and familiarity with the overall NAND market to your best advantage.

Features		Benefits
Density	MLC: 64Gb–256Gb SLC: 32Gb–128Gb	Industry-leading densities
Endurance	MLC: 30,000 WRITE/ERASE cycles SLC: 300,000 WRITE/ERASE cycles	High-endurance enables applications that require intensive program and erase operation while prolonging memory life
Interface	ONFI 2.1	Synchronous interface provides increased bandwidth and trasfer ray
Temperature Range	-40°C to +85°C	Wide temperature range is ideal for transaction-intensive applications
Configuration	x8	Industry-standard configuration enables easy system design
Package	BGA	Industry-standard packaging enables easier density migration

Choosing the Right NAND
Weighing the advantage of each NAND Flash memory solution is important if you’re going to find the best possible device for your application. To help, we’ve developed a Choosing the Right NAND guide, which offers a basic overview of the various forms of NAND Flash memory available to system designers, enumerating the features and benefits of each.

View the guide

Title & Description	ID#	Updated	Size
ONFI 2.0: High Speed NAND Overview: Discusses the limitations of the NAND interface and how ONFI 2.0 helps overcome performance limitations and provide greater scalability. Presented by Applications Engineering Manager and ONFI Technical Team Member, Michael Abraham.		11/2007	163KB
Enterprise NAND Flash Memory Flyer: Discusses features and advantages of Micron Enterprise NAND Flash memory.		8/2010	153KB
ONFI Flyer:		6/2009	166KB
HD-SIM White Paper:		12/2009	2MB
NAND Flash Performance Increase : Customers using the PAGE READ CACHE MODE operation provided in Micron NAND Flash devices will realize significant performance gains in systems requiring increased data volume at a much faster rate.	TN-29-01	5/2007	211KB
Small Block vs. Large Block NAND Devices: Large-block NAND Flash devices offer significant performance increases over their small-block NAND Flash counterparts for READ, PROGRAM, and ERASE operations.	TN-29-07	5/2007	397KB
Hamming Codes for NAND Flash Memories: Outlines hamming codes NAND Flash memory	TN-29-08	5/2007	235KB
NAND Flash Security: Using Micron NAND Flash security features to implement component and code authentication security solutions, designers can protect critical system components and proprietary system software from unwanted attacks and alterations.	TN-29-11	5/2007	194KB
Monitoring Ready/Busy Status in 2, 4, and 8Gb Micron NAND Flash Devices: Four options for determining the NAND Flash ready/busy device status are presented with detailed explanations of each option.	TN-29-13	5/2007	98KB
NAND Flash Performance Increase with PROGRAM PAGE CACHE MODE Command: This technical note discusses the benefits of PROGRAM PAGE CACHE MODE operations over normal PROGRAM PAGE operations. It also provides specific timing examples and instructions for performing PROGRAM PAGE CACHE MODE operations. Rev. C	TN-29-14	2/2010	273KB
Boot-from-NAND Using Micron MT28F1G08ABA NAND Flash with the Texas Instruments™ OMAP™ 2420 Processor: Describes Boot-from-NAND using Micron MT29F1G08ABA NAND Flash with the Texas Instruments™ OMAP™ 2420 processor.	TN-29-16	6/2007	446KB
Booting from Embedded MMC: Describes booting from an embedded ARM processor in the MMC environment	TN-29-18	6/2008	289KB
NAND Flash 101 - An Introduction to NAND Flash and How to Design It In to Your Next Product: Provides an introduction to NAND Flash and how to design it into your next product. Rev. B	TN-29-19	4/2010	992KB
TN-29-24: Micron Wire-Bonding Techniques: Describes wire-bonding techniques.	TN-29-24	12/2009	178KB
Improving NAND Flash Performance Using Two-Plane Command Enabled Micron Devices: Describes the performance benefits of Micron two-plane commands, and provides implementation guidelines for making the best use of two-plane capabilities	TN-29-25	9/2008	126KB
NAND Flash Status Register Response in Cache Programming Operations: Describes status register responses when operating in cache programming modes	TN-29-26	6/2007	260KB
Memory Management in NAND Flash Arrays: Describes common NAND Flash memory-management methods for effective use of the NAND Flash memory array	TN-29-28	12/2009	278KB
Using COPYBACK Operations to Maintain Data Integrity in NAND Flash Devices: Describes how to use COPYBACK operations in NAND Flash devices	TN-29-41	10/2008	104KB
Wear-Leveling Techniques in NAND Flash Devices: Highlights the importance of wear leveling, explains two wear-leveling techniques, and discusses implementing wear leveling	TN-29-42	10/2008	275KB
NAND Flash Performance Improvement Using Internal Data Move: NAND data management capabilities and higher system performance through NAND Flash internal data moves	TN-29-15	3/2010	224KB
Bypass Capacitor Selection for High-Speed Designs: Describes bypass capacitor selection for high-speed designs.	TN-00-06	12/2009	490KB
IBIS Behavioral Models: Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site.	TN-00-07	11/2009	168KB
Thermal Applications: Defines a general method and criteria for measuring and ensuring that Micron components and modules do not exceed the maximum allowable temperature	TN-00-08	5/2010	258KB
Understanding the Quality and Reliability Requirements for Bare Die Applications: Describes the quality and reliability requirements for bare die applications	TN-00-14	10/2009	156KB
Recommended Soldering Parameters: Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products.	TN-00-15	3/2007	71KB
Uprating of Semiconductors for High-Temperature Applications: Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer’s environmental specifications	TN-00-18	5/2010	439KB
Understanding Signal Integrity: Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life	TN-00-20	12/2009	2MB
SEMI Wafer Map Format: Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI®). With SEMI formatting, Micron’s customers can be confident they will always receive consistent, compatible, reliable map files.	TN-00-21	2/2009	113KB
Thinning Considerations for Wafer Products: Information on optimal wafer-thinning processes to meet specific customer requirements	TN-00-19	10/2009	75KB
Next-Generation NAND Flash Part Numbering System: Part numbering guide for Micron Next-Generation NAND Flash products.		8/2009	37KB
Standard NAND Flash Part Numbering System: Part numbering guide for Micron Standard NAND Flash products.		2/2009	29KB
Flash Memory Technology Direction: This paper explains the trade-offs associated with available disk caching methods, the differences between various types of Flash memory, and the advantages that NAND offers when superior performance is critically important.		12/2009	659KB
Product Marks/Product and Packaging Labels: Explains product part marking, and product and packaging labels.	CSN-11	2/2010	580KB
PCN/EOL Systems: Explains Micron's product change notification and end-of-life systems.	CSN-12	8/2009	77KB
Wafer Packaging and Packaging Materials: Provides complete shipping and recycling information about each of the materials used for shipping Micron® products.	CSN-20	3/2010	587KB
Bare Die SiPs and MCMs: Describes design considerations for bare die SiPs and MCMs.	CSN-18	4/2009	155KB
Shipping Quantities: Provides tables of part quantity.	CSN-04	3/2010	515KB
Micron Component and Module Packaging: Explanation of Micron packaging labels and procedures.	CSN-16	3/2010	833KB
ESD Precautions for Die/Wafer Handling and Assembly: Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs.	CSN-24	8/2010	122KB
Electronic Data Interchange: Describes EDI transmission sets, protocol, and contacts.	CSN-06	9/2005	55KB
RMA Procedures for Packaged Product and Bare Die Devices: Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs.	CSN-07	8/2004	52KB
Environmental Programs: Describes the environmental programs at Micron, including air quality, pollution prevention, reclamation and reuse, and waste recycling and reduction.	CSN-05	6/2004	55KB
ISO System Management Standards: Describes ISO system management standards.	CSN-08	4/2004	40KB
ONFI Standards and What They Mean to Designers: Inconsistencies without ONFI and results with ONFI		12/2009	170KB
Optimizing NAND Flash Performance: Improving NAND performance in various applications		12/2009	153KB
A Closer Look at NAND Flash: Exploring the possibilities of SSDs		12/2009	3MB
The Inconvenient Truths of NAND Flash Memory: Overview of NAND Flash		12/2009	353KB
Overcoming (or Embracing) the Dreaded Single-Source Dilemma: Multisourcing versus single-sourcing		12/2009	247KB
NAND Flash Reliability and Performance - The Software Effect: NAND software		12/2009	303KB
Introduction to Flash Memory: Basics of Flash memory		12/2009	1MB
Power Requirements for Multi-Bit Per Cell NAND Flash: Technology differences, power consumption considerations		12/2009	93KB
3-Bit/Cell NAND Flash: Architecture, performance, endurance, system requirements, cost advantages, applications		12/2009	93KB
NAND Flash Consideratons for Consumer Applications: NAND requirements/system reliability in consumer applications		12/2009	717KB
Improving Power Budgeting Estimates in NAND Applications: Measuring Icc with better predictability		12/2009	711KB
The Many Flavors of NAND...and More to Come: Keynote for Flash Memory Summit 2009		12/2009	8MB
NAND Flash Architecture and Specification Trends: How to prepare for changes brought on by technology shrinks		12/2009	713KB
An ONFI Update: Overview of enhancements and the path to higher performance		12/2009	1MB
Choosing the Right NAND for Your Application: Market overview, traditional versus newer devices, and Micron's broad product offering		12/2009	3MB
NAND On-Die ECC: In this webinar, learn about the latest family line of NAND products that supports on-die ECC. We’ll show you how to take advantage of the built-in ECC, which will enable your older controllers to support the latest NAND technology. In addition, we’ll provide details of the two interface types offered: the traditional parallel ONFI 1 interface or the serial NAND interface, which uses the serial peripheral interface (SPI) bus.		1/2010	0B
ONFI Update: Listen as Jim Cook, Micron’s NAND guru, discusses the evolution of ONFI standards. He’ll start with the original ONFI 1.0 asynchronous standard, and then talk about the source synchronous interface of ONFI 2.0 through ONFI 2.2. His final thoughts will provide a glimpse into the future of ONFI 3 with its targeted 400 MB/s speed extensions.		1/2010	0B
Micron® ECC Module for NAND Flash via Xilinx® Spartan™-3 FPGA: Micron® ECC module was developed and tested using Xilinx® Spartan™-3 and can be ported to certain other platforms of the user’s choosing.	TN-29-05	5/2007	1MB
Micron® NAND Flash Controller via Xilinx® Spartan™-3 FPGA: Describes the Micron NAND Flash controller, techniques for interfacing the NAND Flash device with a processor, and use of the Micron glueless interface to interface a processor with NAND Flash memory.	TN-29-06	6/2007	893KB
FBGA Date Codes: Date codes for FBGA-packaged components		8/2005	23KB
Designing in NAND Flash – Webinar: This webinar is intended for engineers who want to learn more about the architectures, features, and performance aspects of NAND Flash memory. Micron’s Jim Cooke provides an in-depth look at the device technology and challenges associated with MLC NAND Flash, along with comparisons and decision-making criteria for designing with SLC versus MLC NAND Flash. He also discusses several factors that can affect the reliability of your NAND solution and how to best alleviate them.		4/2007	0B
NAND Flash Controller on Spartan-3: This technical note describes the Micron NAND Flash controller, techniques for interfacing the NAND Flash device with a processor and use of the Micron glueless interface to interface a processor with NAND Flash memory.	TN-29-06	6/2007	893KB
ECC Module for Xilinx Spartan-3: Describes the Micron® ECC module that was developed and tested using Xilinx® Spartan™-3 and can be ported to certain other platforms of the user’s choosing.	TN-29-05	5/2007	1MB
Determining NAND Flash Ready/Busy Status: Systems that utilize NAND Flash memory can use either the ready/busy pin or the status register to determine whether a Micron® NAND Flash device is busy or ready to accept a new command. This technical note addresses the use of status register bit 5, which indicates the ready/busy status of the NAND Flash device.	TN-29-13	2/2010	140KB
Avoid Counterfeit Products: Highlights Micron-guaranteed products and how to buy genuine Micron products.		3/2010	201KB
Migrating from 50-Series to 60-Series SLC NAND Flash Devices: Migrating from 50-Series to 60-Series SLC NAND Flash Devices; M58A, M59A, M50A, M68A, M69A, M60A	TN-29-51	6/2010	132KB
TN-29-52: Migrating 1Gb 48nm and 2Gb/4Gb 57nm SLC NAND Flash Memory to 34nm: Provides guidelines for migrating 1Gb 48nm and 2Gb/4Gb 57nm SLC, large-page NAND Flash memory to 34nm technology (M60A, M69A & M68A)	TN-29-52	7/2010	190KB

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Do you support small block devices?: Currently, Micron only offers large block devices. Please refer to Technical Note, TN29-07 - Small Block vs. Large Block NAND Devices.
How do I achieve greater PROGRAM/READ throughput for the NAND device?: To get the maximum PROGRAM/READ throughput for Micron NAND Flash devices, use the PROGRAM and READ CACHE operations. See the NAND device data sheet and our NAND Technical Notes Page for details on how to use these commands.
How is High-Speed NAND different from traditional NAND?: High-Speed NAND can read data at speeds up to 200 megabytes per second (MB/s) and can write data at speeds up to 100 MB/s. These speeds are achieved by leveraging the new ONFI 2.0 interface specification and a four-plane architecture with higher clock speeds. In comparison, conventional SLC NAND is limited to 40 MB/s for reading data and less than 20 MB/s for writing data. To maximize the performance benefits of High-Speed NAND, users must use the new ONFI 2.0 synchronous interface standard.
How is Nvb specified?: Nvb is specified as the minimum number of valid blocks at the end of the P/E cycle spec.
How much ECC do I need to support your devices?: We define our ECC requirement per 512-byte section. MLC NAND devices have a higher ECC requirement than SLC NAND due to the increased number of bits per cell. ECC requirements differ for designs, so consult the device data sheet for the amount of ECC needed.
I am seeing a lot of READ DISTURB errors. Can you tell me if there is a problem with your part?: READ disturb occurs when the same data is read repeatedly. By its nature, NAND technology has a very low occurrence of read-disturb errors. But, to mitigate any errors received due to read disturb, we recommend that users refresh the data to reduce the amount of times the same data is read.
I am using the correct amount of error correction code (ECC) for the NAND device, but I’m still seeing bit/byte errors in data I read back from the NAND device.: Make sure that you are issuing a READ STATUS command to the NAND device after any type of PROGRAM or ERASE operation. Checking status after a PROGRAM or ERASE operation will report whether the PROGRAM or ERASE operation was successful. If the READ STATUS command reports a failure with a PROGRAM operation, that data should be programmed somewhere else and the block being programmed should be retired. If the READ STATUS command reports a failure with an ERASE operation, that block should also be retired.
I’ve heard that NAND has too many errors to boot from. Is this true?: With ECC, NAND can achieve bit error rates (BER) that are comparable with NOR, which is commonly used as a booting device. Applications that use NAND typically copy the booting code to DRAM and execute from DRAM. For more information, read Technical Note 29-16, which is geared to a specific processor, but the concepts can be applied generally. Technical Note 29-19 is a very useful technical note on the general concepts of NAND.
Is High-Speed NAND a proprietary or patented technology?: High-Speed NAND leverages the ONFI 2.0 standard synchronous interface to achieve its breakthrough performance. Host controllers can design-in High-Speed NAND with confidence knowing that ONFI 2.0 is an industry-standard interface that will be supported by other NAND architectures and devices. In addition, because ONFI 2.0 is backward-compatible with ONFI 1.0, designing in ONFI 2.0 is always a safe choice.
Should I be marking blocks bad due to READ errors?: Yes.
What NAND parts have been validated with the OMAP™35x?: Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support.
When I issue a Read ID command (90h) to a two-die NAND device, I get a device ID back that states it is a one-die NAND device.: In a two-die NAND device, where a single die is on each CE#, the device ID that is returned is per CE# for one die. For example, an 8Gb two-die NAND device with two CE# pins would return a 4Gb device ID on each CE#. See the Read ID section of the NAND device data sheet for more details.
Where can I find additional technical information about Micron NAND devices that is not covered in the device data sheets?: Additional Micron NAND Flash technical information—including details on performance enhancing commands—can be found on the NAND Flash Technical Notes page.
Where can I find simulation models for NAND Flash devices?: Micron posts Verilog, HSPICE, and IBIS models for NAND devices. To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.
Why am I getting a bit/byte error reading back the information I programmed into the NAND device?: Check that you are using the appropriate amount of error correction code (ECC) for the NAND device. The ECC threshold can be found in the "Error Management" section of the NAND device data sheet. Also ensure that none of the bad blocks marked by the NAND manufacturer (Micron) are used. See the "Error Management" section of the NAND device data sheet for more details on how to search for manufacturer-marked bad blocks.
Why doesn't the NAND Flash device respond correctly to commands issued to it?: Be sure you are issuing a reset command (FFh) to the NAND device after powering on the device. A reset command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.
Will High-Speed NAND require new types of controllers?: To take full advantage of the capabilities of our High-Speed interface, controllers need to support the latest ONFI industry standard.
We have an MMC host controller which supports v4.1 or earlier. Can we use a v4.2 e·MMC device?: Yes, if the device density is up to 2GB. However, for 4GB and higher densities, you need to have the v4.2 MMC driver software in your system, because the device uses sector address mode which is defined in the v4.2 specification.
We have an SD/MMC card socket but don’t have a BGA socket to evaluate an e·MMC device. Can we evaluate a Micron e·MMC device?: Yes, Micron can provide a small board with a mounted BGA device that can fit into an SD/MMC standard card socket for use in evaluation.
Does Micron e·MMC support SPI mode?: Unfortunately, Micron e·MMC does not support SPI mode. The JEDEC e·MMC standard specification removed this functionality from the v4.3 specification.
What is the purpose of R_OD resister? Why do we need to prepare R_OD and R_CMD on command line?: R_OD resister is only used during the card identification period to support 400 kHz clock operation. During this period, the device uses an open drain driver which does not have pull-up capability. The host needs to have strong pull-up capability to operate the command line at 400 kHz. This must be disconnected after the card identification period. R_CMD is used to keep the command line high when there is no transaction on the command line. If the host does not have R_OD, the R_CMD can be used instead. However, the maximum operating frequency during the card identification mode must be reduced.
Is v4.4 e·MMC function backward compatible to v4.2 function?: Yes, v4.4 function is backward compatible to v4.2 function. The v4.2 MMC host can use the v4.4 e·MMC device with v4.2 functionality. The v4.4 device has several additional features which are suitable for secure boot applications from e·MMC devices.

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