Mini-DIMMs: Great Signal Integrity in a Small Module
Our DDR2 and DDR3 Mini-DIMMs are available in a range of densities and configurations to suit a variety of designs. All of our Mini-DIMMs come with ECC to ensure the data integrity that helps make them the foundation for reliable high performance in networking platforms.
A Networking-Specific Solution
With our Mini-DIMMs, you get all the benefits of our DRAM design and manufacturing expertise plus our high-quality test methodology—enabling you to design smaller form factor routers, switches, bridges, and hubs that can deliver peak performance.
ECC for Excellent Data Integrity
All of our Mini-DIMMs feature built-in ECC to ensure reliably high data integrity. Registered versions also include address parity, which provides additional performance for systems where data accuracy is especially critical. Address parity is supported by some controllers and goes a step further than ECC by allowing the system designer to verify the accuracy of the address lines to the module.
Industry-Leading Quality
We develop and build high-quality networking modules, managing the module manufacturing process from beginning to end. We design with leading-edge DRAM and work with board makers and industry organizations. We carefully test components, packaging, and modules. Our involvement at every stage of memory development and manufacture ensures you'll consistently receive top-quality Mini-DIMMs.
Features
Benefits
Wide Density Range
With many density choices in a small form factor, you can build powerful devices in a limited amount of space
Flexible Configuration
Available as registered or unbuffered* in single- or dual-rank configurations (*UDIMMs in DDR3 only)
ECC
ECC bits to support error handling and correction for increased data reliability
Optional PLL & buffer
Reduces the load on the memory controller, which ensures signal integrity and enables the system to accommodate the maximum number of modules
Simulation Models
Our convenient thermal and electrical simulation models are available online for easy download
Thermal Applications:
Defines a general method and criteria for measuring and ensuring that Micron components and modules do not exceed the maximum allowable temperature
TN-00-08
5/2010
258KB
Recommended Soldering Parameters:
Defines the recommended soldering techniques and parameters for
Micron Technology, Inc., products.
Understanding Signal Integrity:
Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life
TN-00-20
12/2009
2MB
Memory Module Serial Presence-Detect:
Describes how SPD is essential in helping to standardize the configuration, timing, and manufacturing information of memory modules
ESD Precautions for Die/Wafer Handling and Assembly:
Describes the benefits of controlling ESD in the workplace, including higher yields and improved
quality and reliability, resulting in reduced manufacturing costs.
Environmental Programs:
Describes the environmental programs at Micron, including air quality, pollution prevention, reclamation and reuse, and waste recycling and reduction.
Moisture Absorption in Plastic Packages:
Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture
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Can Vtt and Vref be supplied by the same supply in my system design?
With proper decoupling this can be an acceptable design. However, Micron recommends ensuring all supplies are separated. Vref tends to have more noise on it because it supplies signals that are regularly switching. A robust design would typically not connect these supplies due to the possibility of introducing this noise onto the Vtt plane which should be as stable as possible. Additionally, Vref requires much less current than Vtt.
Is there a set of trace lengths and routing rules that are standard for use when designing a system that uses a specific module technology and form factor?
No. A robust memory subsystem design that includes the use of 1 or more memory modules must be simulated in order to determine the optimum trace lengths, terminations. However, our design guides such as TN-47-01 and TN-41-08 have some best practices and design examples based on some typical system assumptions. This information is not meant to be the only way your system can be designed. It is a starting point and moreover an example of the steps used to determine the best design for your system.
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