DDR3 SDRAM

DDR3 SDRAM

Market-Leading Technology

By pushing the envelope in key areas like power consumption, signaling speeds, and bandwidth, our DDR3 brings new levels of performance to desktop, notebook, and server computing systems.

Tech BurstMicron DDR3 – Industry-Leading Performance and Support

DDR3 is the next-generation, high-performance solution for CPU systems—it pushes the envelope in key areas like power consumption, signaling speeds, and bandwidth, bringing new levels of performance to desktop, notebook, and server computing. DDR3 supports data rates of 1066 to 1600 MT/s, with clock frequencies of 533 to 800 MHz, respectively—effectively doubling the speed of DDR2. DDR3's standard 1.5V supply voltage cuts power consumption by up to 30% over DDR2.

DDR3 also brings new levels of power efficiency—our standard 1.5V supply voltage cuts power use by up to 30% over DDR2, while our 1.35V parts shave another 20% off standard 1.5V consumption.

When you’re ready to make a move to DDR3, we’ll be here to help. As an industry leader we are expertly equipped to help you sort through the technical details and recommend the best DDR3 solution for your application.

DDR3 SDRAM Part Catalogs and Documentation


Balancing Power and Performance for Tablet and Ultrathin-Client Computing
Tablets and thin-clients are changing the landscape of computing—and memory requirements, too. These powerful, highly mobile personal computing devices walk a fine line between memory-performance needs and battery-life limits, not to mention space constraints. Our new 1.35V DDR3Lm specifically targets the ultrathin-client market with an optimal combination of high performance (data rates up to 1600 MT/s), low power usage (with tight IDD6 specs, 50% self refresh power savings versus standard DDR3L, and TCSR enablement), cost efficiency, and footprint size (x32 options)—the best of LPDDRx and DDRx technologies, blended into one.

Feeding Memory-Hungry Systems
If your new hardware design is primed for higher performance, we've got you covered. Our DDR3 is ready for the memory demands of next-generation systems. The increased bandwidth is significant, with speeds up to 1600 Mb/s. At peak performance, the data transfer rate is equivalent to transferring a 100,000-page document in about one second.

Features Benefits
Package FBGA Enables better electrical performance and speed
Pinout Improved pinout Improves signal integrity, power and ground distribution, and reliability
Voltage 1.35V, 1.5V Reduces memory system power demand
Densities 1Gb, 2Gb, 4Gb Enables large memory subsystems
Internal Banks 8 Provides better back-to-back access and performance
Speed DDR3-1066, DDR3-1333, DDR3-1600 Provides migration path for higher bus speeds
Termination DRAM on-die termination (ODT) Improves write signaling
Data Strobes Differential or single-ended Improves system timing margin by reducing strobe crosstalk
Leveling Improved read/write leveling Allows better control of time delta, data capture, and receiver timing
System Synchronization Master reset Improves stability

Type Secure Title & Description ID# Updated Size
IBIS Behavioral Models:  Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 163.98 KB
Thermal Applications:  Defines a general method and criteria for measuring and ensuring that Micron components and modules do not exceed the maximum allowable temperature TN-00-08 05/2010 252.18 KB
Understanding Quality and Reliability Requirements for Bare Die Applications:  Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 152.83 KB
Recommended Soldering Parameters:  Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 03/2007 69.09 KB
Uprating of Semiconductors for High-Temperature Applications:  Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 428.33 KB
Understanding Signal Integrity:  Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 1.52 MB
SEMI Wafer Map Format:  Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 02/2009 110 KB
Thinning Considerations for Wafer Products:  Information on optimal wafer-thinning processes to meet specific customer requirements TN-00-19 10/2009 73.58 KB
DDR3 Power:  Estimates, effects of bandwidth, and comparisons to DDR2 12/2009 598.62 KB
DDR3 RDIMMs Channel:  Basics, topology, simulations, and timing 12/2009 1.15 MB
Server Memory Solutions for the Impending Data Center Power Crisis:  Facts about data center energy consumption and information about how to achieve significant power savings with Micron's low-voltage memory modules for servers. White Paper 12/2009 309.03 KB
DDR3 Thermals:  Thermal limits, operating temperatures, tools, and system development 12/2009 1.32 MB
DDR3 - What's New:  Technology trends, market forecast, road maps 12/2009 404.43 KB
PCN/EOL Systems:  Explains Micron's product change notification and end-of-life systems. CSN-12 08/2009 75.58 KB
Wafer Packaging and Packaging Materials:  Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 09/2011 776.24 KB
Bare Die SiPs and MCMs:  Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 151.06 KB
Shipping Quantities:  Provides tables of part quantity. CSN-04 10/2011 463.55 KB
Micron KGD Definitions:  Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 65.52 KB
Proper Handling Procedures for Modules:  Includes procedures for how to properly handle modules. CSN-23 12/2007 1.02 MB
Micron Component and Module Packaging:  Explanation of Micron packaging labels and procedures. CSN-16 02/2012 840.61 KB
ESD Precautions for Die/Wafer Handling and Assembly:  Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 119.08 KB
Electronic Data Interchange:  Describes EDI transmission sets, protocol, and contacts. CSN-06 09/2005 53.5 KB
RMA Procedures for Packaged Product and Bare Die Devices:  Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 10/2010 82.64 KB
ISO System Management Standards:  Describes ISO system management standards. CSN-08 04/2004 39.18 KB
The Future of Memory and Storage:  Overview of trends for main memory and Flash memory 12/2009 1.54 MB
Main Memory Technology Direction:  Technology trends, customer requirements, intro to DDR3 12/2009 531.53 KB
Calculating Memory System Power For DDR3 :  Details how DDR3 SDRAM consumes power and provides the tools that system designers can use to estimate power consumption. TN-41-01 05/2007 1.12 MB
DDR3 ZQ Calibration:  Describes how the DDR3 SDRAM driver design has been enhanced TN-41-02 02/2008 250.61 KB
DDR3 Dynamic On-Die Termination :  With DDR3, dynamic ODT provides systems with increased flexibility to optimize termination values for different loading conditions TN-41-04 03/2008 370.26 KB
DDR3 Termination Data Strobe :  Provides guidelines for using the TDQS feature to reduce signal integrity issues associated with mismatched DQS loading in in combined x4-based/x8-based systems TN-41-06 03/2008 152.41 KB
DDR3 Power-Up, Initialization, and Reset:  Describes power-up, initialization, and reset with DDR3. TN-41-07 10/2008 504.77 KB
DDR3 SDRAM System-Power Calculator:  Version 0.9 12/2010 195.3 KB
DRAM Component Part Numbering System:  Part numbering guide for DDR3/DDR2/DDR/SDR SDRAM, Mobile LPDRAM, and RLDRAM components 02/2012 39.77 KB
FBGA Date Codes:  Date codes for FBGA-packaged components 08/2005 22.36 KB
Accelerate Design Cycles with Simulation Models:  Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 206.91 KB
Design Guide - Dealing with DDR2/DDR3 Clock Jitter:  Explores DDR2/DDR3 clock jitter specifications and provides guidance on how to apply them and how to deal with violations TN-04-56 09/2008 272.53 KB
Micron Wire-Bonding Techniques:  This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 66.13 KB
Industrial and Multi-Market Applications Flyer:  Our extensive and stable portfolio of IMM-focused memory solutions empower technology developments in automotive, industrial, medical, manufacturing, and other multi-market segments. Product Flyer 08/2011 593.95 KB
Micron BGA Manufacturer's User Guide:  Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 07/2011 353.32 KB
DDR3L SDRAM System-Power Calculator:  07/2011 197.81 KB
Product Marks/Product and Packaging Labels:  Explains product part marking, and product and packaging labels. CSN-11 02/2012 666.83 KB
DDR3 Advantages Presentation:  Covers power, speed, performance, and more 12/2009 365.19 KB
Bypass Capacitor Selection for High-Speed Designs:  Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 481.9 KB

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Can I run Micron’s DDR3 memory at clock speeds slower than 300 MHz?
Yes. Micron supports the optional feature to disable the DLL. This feature allows the DRAM to operate at frequencies slower than 125 MHz. A minimum clock rate is not specified, but the timing still must satisfy the refresh interval (tREFI). When operating in DLL disable mode, special conditions apply: - no support of on-die termination (ODT); ODT must be disabled or turned off - both CL and CWL must be equal to 6 - data out is no longer edge-aligned to the clock and read latency will be AL + CL - 1 tCK
How do I determine my CAS WRITE latency (CWL)?
In DDR3, only one CWL is valid for a given clock frequency range. - tCKavg = 2.5ns to <3.3ns, CWL = 5 - tCKavg = 1.875ns to <2.5ns, CWL = 6 - tCKavg = 1.5ns to <1.875ns, CWL = 7 - tCKavg = 1.25ns to <1.5ns, CWL = 8
How do I determine the amount of time between ZQCS commands?
Each ZQCS command can correct a minimum of 0.5 percent impedance error within 64 clocks. To calculate the ZQCS interval, use the following formula: ZQCS Interval =ZQCorrection (Tsens x Tdriftrate) + (VSens x Vdriftrate) For the sensitivities, use the MAX number from the ODT voltage and temperature sensitivity table in the component specification. Drift rates will vary from system to system. ZQCorrection equals 0.5%/64 clocks.
What component densities are available?
JEDEC has defined DDR3 densities of 512Mb–8Gb; Micron plans to support 1Gb through 4Gb.
What is burst chop?
Due to DDR3's use of the 8n-prefetch architecture, a true burst of 4 is not possible with most designs. Burst chop mode (BC4) is unique to DDR3. In this mode, the last 4 bits of the burst are essentially masked. Timing in BC4 cannot be treated like a true BL4. For READ-to-WRITE, select WRITE-to-READ, and select WRITE-to-PRECHARGE transitions, the system can achieve clock savings in the BC4 mode. While doing READ-to-READ or WRITE-to-WRITE transitions, timing must be treated like BL8; no clock savings will be realized.
What is Dynamic ODT?
Dynamic ODT (Rtt_WR) enables the DRAM to change termination values during a WRITE without having to perform a MODE REGISTER SET command. When Rtt_Wr and Rtt_Nom are both enabled, the DRAM will change termination values from Rtt_Nom to Rtt_Wr at the beginning of the WRITE burst. Once the burst is complete, the termination will be changed back to the Rtt_Nom value. Rtt_Wr can be used independently of Rtt_Nom, but termination will be on WRITEs only.
What is the difference between the ZQCL and ZQCS commands?
ZQCL stands for ZQ calibration long. This command must be issued during the power-up and initialization sequence and requires 512 clocks to complete. After power-up and initialization, the command can be issued any time the DRAM is idle. These subsequent commands only require 246 clocks. This command is used when there is more impedance error correction required than a ZQCS can provide. ZQCS stands for ZQ calibration short. This command can be performed any time the DRAM is idle. One ZQCS can correct a minimum of 0.5 percent impedance error and requires 64 clocks.
What is the "MPR"?
MPR is a multi-purpose register. It is a specialized register designed to allow predefined data to be read out of the DRAM. Data is one bit wide and is output on a prime DQ. For Micron DDR3 parts, the prime DQs are DQ0 for x4/x8 and DQ0/DQ8 for x16. Two locations in the MPR are defined. One allows the readout of predefined data burst—in this case, 01010101. The other location is used to output the refresh trip points from the on-die thermal sensor.
What is the operating voltage?
DDR3 operates at Vdd = VddQ = 1.5V ±0.075V.
What is the output driver impedance for DDR3?
The default output driver impedance for DDR3 is 34 ohms. The impedance is based on calibration to the external 240 ohm resistor, RZQ.
What is the RESET# pin used for?
RESET# is the master reset for the DRAM. It is an active LOW, asynchronous input. When the RESET# is asserted, the DRAM outputs and ODT will tri-state. The DRAM counters, registers, and data will be unknown. A RESET must be performed as part of the power-up and initialization sequence. During this sequence, the RESET# must remain LOW for a minimum of 200µs. After power-up and initialization, RESET# may be asserted at any time. Once asserted, it must stay LOW for a minimum of 100ns and a full initialization of the part must be performed afterward.
What is "write leveling"?
For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks. Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM. Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM. A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
What is "ZQ Calibration"?
The ZQ calibration command can calibrate the DRAM's output drivers (Ron) and ODT values (Rtt) over process, voltage, and temperature when a dedicated 240 ohm (±1 percent) resistor is connected from the DRAM's ZQ pin to ground. In DDR3, two different calibration commands exist: ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). ZQCL is normally used during power-up initialization and reset sequences, but may be issued at any time by the controller, depending on the system environment. ZQCS is used to perform periodic calibrations to account for small voltage and temperature variations; it requires a smaller timing window to complete.
Will Micron support an extended temperature range for DDR3?
Yes. Micron DDR3 parts will support a Tcase of 0°C to 95°C.

DDR3 SDRAM

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