DDR SDRAM

DDR SDRAM

DDR: Still an Ideal Choice for Many New Designs

When we introduced DDR SDRAM, it was a revolutionary and pioneering technology—enabling applications to transfer data on both the rising and falling edges of a clock signal—and vastly improving performance over SDRAM. And because DDR continues to be an ideal choice for many new designs, we’re committed to supporting it for the long term.

motherboard blueDoing More to Meet Mainstream Memory Needs

Long-Term DDR Support
We know that many of our customers will continue to use DDR solutions in their designs well into the future. We’re committed to leveraging our proven technology, premier quality, and industry-leading manufacturing efficiencies to provide DDR for many years to come.


DDR SDRAM Part Catalog and Documentation


Detailed, Specific Technical Help
We strive to provide the best technical support in the memory business, bar none. From FAEs, tech notes, and data sheets, to simulation models, calculators, and development tools—our goal is to help you integrate the industry’s highest-quality memory with ease.

DDR SDRAM Toolbox
Our DDR SDRAM toolbox is a centralized repository of technical resources to help designers who are developing system-level products that use DDR. From here, you can access our DDR tech notes, our DDR system power calculator, a list of qualified Micron/motherboard combinations, and other standards and specifications.

DDR SDRAM Toolbox

RoHS 5/6 and 6/6
A complete portfolio of RoHS 6/6-compliant DDR parts, plus a set of 5/6-compliant products for those industries with exempt applications, gives customers a choice.

Extended Operating Temperatures
Extended operating temps ensure superior performance in high-stress networking, communication, industrial, and automotive environments.

Specification Description
Densities 256Mb, 512Mb, 1Gb
Configuration x4, x8, x16
Supply Voltages 2.5, 2.6V
Clock Frequencies 133–200 MHz
Data Rate DDR-266 to DDR-400B
Temperature Ranges 0°C to +70°C, 
–40°C to +85°C
–40°C to +105°C
Packages 54-, 60-ball FBGA 
66-pin TSOP

Type Secure Title & Description ID# Updated Size
IBIS Behavioral Models:  Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 163.98 KB
Thermal Applications:  Defines a general method and criteria for measuring and ensuring that Micron components and modules do not exceed the maximum allowable temperature TN-00-08 05/2010 252.18 KB
Understanding Quality and Reliability Requirements for Bare Die Applications:  Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 152.83 KB
Recommended Soldering Parameters:  Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 03/2007 69.09 KB
Uprating of Semiconductors for High-Temperature Applications:  Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 428.33 KB
Understanding Signal Integrity:  Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 1.52 MB
SEMI Wafer Map Format:  Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 02/2009 110 KB
Thinning Considerations for Wafer Products:  Information on optimal wafer-thinning processes to meet specific customer requirements TN-00-19 10/2009 73.58 KB
Decoupling Capacitor Calculation for a DDR Memory Channel:  Provides a decoupling capacitor calculation for a DDR memory channel TN-46-02 12/2004 151.37 KB
Calculating DDR Memory System Power:  Describes how to calculate DDR memory system power. TN-46-03 03/2005 336.91 KB
General DDR SDRAM Functionality:  Describes DDR SDRAM functionality TN-46-05 12/2001 254.8 KB
Termination for Point-to-Point Systems:  Provides a basic understanding of transmission line theory that is important to insure signal integrity in today's high-speed digital systems. TN-46-06 03/2011 356.29 KB
DDR333 Design Guide for Two-DIMM Unbuffered Systems:  Describes DDR333 design guide for two-DIMM unbuffered systems TN-46-07 12/2002 5.93 MB
Designing for 1Gb DDR SDRAM:  Provides system designers with essential information relevant to utilizing the 1Gb double data rate (DDR) synchronous dynamic random access memory (SDRAM). TN-46-09 11/2009 175.43 KB
DDR SDRAM Point-to-Point Simulation Process:  Covers rarely addressed areas of the DDR SDRAM point-to-point simulation process TN-46-11 07/2005 330.05 KB
Power-Saving Features of Mobile LPDRAM:  Addresses the power-saving features and power calculations of low-power Mobile LPDRAM memory TN-46-12 05/2009 255.93 KB
Mobile LPDDR Versus Standard DDR SDRAM:  An overview of the functional and mechanical differences between low-power and standard DDR and a description of exclusive features of LPDDR TN-46-15 12/2007 432.44 KB
Mobile LPDRAM Unterminated Point-to-Point System Design: Layout and Routing Tips:  Provides guidance for the development of multilayer board designs TN-46-19 11/2008 552.55 KB
PCN/EOL Systems:  Explains Micron's product change notification and end-of-life systems. CSN-12 08/2009 75.58 KB
Wafer Packaging and Packaging Materials:  Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 09/2011 776.24 KB
Bare Die SiPs and MCMs:  Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 151.06 KB
Shipping Quantities:  Provides tables of part quantity. CSN-04 10/2011 463.55 KB
Micron KGD Definitions:  Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 65.52 KB
Proper Handling Procedures for Modules:  Includes procedures for how to properly handle modules. CSN-23 12/2007 1.02 MB
Micron Component and Module Packaging:  Explanation of Micron packaging labels and procedures. CSN-16 02/2012 840.61 KB
ESD Precautions for Die/Wafer Handling and Assembly:  Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 119.08 KB
Electronic Data Interchange:  Describes EDI transmission sets, protocol, and contacts. CSN-06 09/2005 53.5 KB
RMA Procedures for Packaged Product and Bare Die Devices:  Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 10/2010 82.64 KB
ISO System Management Standards:  Describes ISO system management standards. CSN-08 04/2004 39.18 KB
Competitive DDR Memory Subsystems:  DDR milestones and platform design 12/2009 2.64 MB
DDR System Design Considerations:  DDR overview 12/2009 3.46 MB
The Future of Memory and Storage:  Overview of trends for main memory and Flash memory 12/2009 1.54 MB
DDR SDRAM System-Power Calculator:  01/2010 55.81 KB
DRAM Component Part Numbering System:  Part numbering guide for DDR3/DDR2/DDR/SDR SDRAM, Mobile LPDRAM, and RLDRAM components 02/2012 39.77 KB
FBGA Date Codes:  Date codes for FBGA-packaged components 08/2005 22.36 KB
Accelerate Design Cycles with Simulation Models:  Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 206.91 KB
Hardware Tips for Point-to-Point System Design:  Provides hardware tips for point-to-point system design, termination, and layout TN-46-14 06/2008 376.6 KB
Initialization Sequence for DDR SDRAM:  Describes the initialization sequence and configurable device parameters. TN-46-08 08/2010 294.95 KB
Design Guide - Dealing with DDR2/DDR3 Clock Jitter:  Explores DDR2/DDR3 clock jitter specifications and provides guidance on how to apply them and how to deal with violations TN-04-56 09/2008 272.53 KB
Micron Wire-Bonding Techniques:  This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 66.13 KB
Industrial and Multi-Market Applications Flyer:  Our extensive and stable portfolio of IMM-focused memory solutions empower technology developments in automotive, industrial, medical, manufacturing, and other multi-market segments. Product Flyer 08/2011 593.95 KB
Micron BGA Manufacturer's User Guide:  Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 07/2011 353.32 KB
Product Marks/Product and Packaging Labels:  Explains product part marking, and product and packaging labels. CSN-11 02/2012 666.83 KB
Bypass Capacitor Selection for High-Speed Designs:  Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 481.9 KB

Please Note: To view Secure Documents (Secure Lock) please log in or click on a secured document to request access.

A customer uses a DDR -6T part at 333 MHz. Can he substitute a faster speed grade part (DDR400, -5B) without encountering problems due to the 2.6V operation? Can the customer run the part at -75 speeds?
Yes, all speed grades are backward-compatible. So, -5B can run at -6T timing and -6T voltage levels (2.5V). At DDR400 speeds, Micron parts require (in compliance with JEDEC standard) Vdd = VddQ = 2.6V ±0.1V. At slower speed grades (DDR333 through DDR200), the Micron parts are backward compatible, only requiring Vdd = VddQ = 2.5V ±0.2V.
Can I get samples?
Yes. Talk to your service representative.
Can you provide a brief description of the necessary circuit functionality we would need to employ to transition from EDO to SDRAM technology?
Synchronous DRAM, as its name suggests, is a synchronous device and is a little different from EDO. SDRAM are directly tied to the same system clock that drives all of the other subsystems. SDRAM uses a dual-bank architecture—an interleave technique that essentially allows one cell to be read while another is being prepared for a cell access. This "cell hopping" eliminates downtime between cell activities and provides good performance improvement. Since the SDRAM will operate at higher speeds, attention needs to be paid to signal layout, including transmission line techniques such as series-terminating resistors. A consequence of signal layout could be noise due to faster clocks, crosstalk, etc. At the very least, an SDRAM controller is necessary for transitioning from EDO to SDRAM technology.
Do I need a separate voltage regulator to supply Vref power?
How Vref is supplied depends on the system design. Many multi-drop systems (where there are several modules and a need for Vtt on the system board) already have a designated voltage regulator for DDR memory. In this case, the voltage regulator may have a dedicated tap for Vref. Other systems that incorporate point-to-point memory typically use a simple voltage divider resistor network between Vdd and Vss.
Does Micron provide VHDL models for DDR parts?
No. Micron no longer supports VHDL models. We can, however, provide a generic 8 Meg x 8 model (MT46LC8M8) that can be scaled to the desired model dimensions. It’s a good starting point for building a compatible DDR model. To obtain this file, contact your Micron representative or a Micron applications engineer. You could also contact Denali or Synopsys to obtain one of their models. Or you could use a suitable multi-language simulator (like Modelsim) that cosimulates Verilog and VHDL and then download our Verilog model.
How long does Micron plan to support 3.3V SDRAM?
Micron has an extensive customer base across all four densities (64–512Mb) of SDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
How long does Micron plan to support DDR?
Micron has an extensive customer base across all four densities (256Mb–1Gb) of DDR and plans to support it for several years. Contact your local Micron sales representative for direction on the preferred part number to qualify.
Is VREF required during self refresh? I would like to put DDR memory in self refresh mode and turn off power to the CPU (the system is battery-operated). Can I disable VREF and still have correct self refresh operation?
Yes. VREF is required during self refresh. All DDR components' on-chip address counters are still operational during self refresh mode, so VDD must be maintained within the stated data sheet limits. Again, VREF must not be disabled after the DDR memory is put into self refresh mode. Doing so could easily result in inadvertently exiting self refresh. You should understand that VREF draws almost no power; any current drawn by VREF is negligible when compared to VTT and the core VDD. DDR components typically use a differential pair common source amplifier as their SSTL_2 input receiver. Because the VREF pin is used primarily as an input to this circuit, its current draw is low. It is so low, in fact, that the device’s input leakage current (~5µA) can be considered the maximum current requirement for the VREF pin. Typical VTT power is drawn from other places on the board and depends on the other components used on the module/system in addition to DRAM devices.
On DDR, can the allowed jitter tolerance be larger than +/-150ps if we use a clock of 120 MHz instead of 133 MHz? Can the allowed jitter tolerance be larger if the device is faster?
The part may have more tolerance or margin to jitter than 150ps at 133 MHz, but Micron still has the same specification for all speeds. Micron does not relax jitter specifications for a lower speed.
On DDR, what happens when DQS write postamble (tWPST) maximum specification is exceeded? What problems could this cause?
The tWPST maximum specification is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
On DRAM, can a READ or WRITE command be given instead of a refresh?
If all of the different row addresses are read or written within the refresh time (tREF), a refresh need not be performed. (The different row addresses are the same number of rows as the number of REFRESH cycles. For example, in the case of 8,192/64ms, the number of rows equal 8,192.) With DRAM, selecting row addresses causes the same action as a refresh, so a REFRESH command need not be executed.
On DRAM, can unused DQ (data) pins be left floating?
Micron recommends that unused data pins be tied HIGH or LOW. Because Micron uses CMOS technology in DRAM manufacturing, letting them float could leave the pins susceptible to noise and create a random internal input level. Unused pins can be connected to VDD or ground through resistors.
What is the difference between no connect (NC), no function (NF), and do not use (DNU) pins? How should external connections to them be handled?
An NC (no connect) pin indicates a device pin to which no internal connection is present or allowed. Micron recommends that no external connection be made to this pin. However, if a connection is inadvertently made, it will not affect device operation. Sometimes NC pins could be reserved for future use. Refer to the part’s data sheet to confirm whether the pin is reserved for future use. An NF (no function) pin indicates a device pin that is electrically connected to the device but for which the signal has no function in the device operation. Micron strongly recommends that no external connection be made to this pin. A DNU (do not use) pin indicates a device pin to which there may or may not be an internal connection but to which no external connections are allowed. Micron requires that no external connection be made to this pin. Refer to the part’s data sheet for more details.
What is the maximum junction temperature at which DDR SDRAM functionality is guaranteed?
Please refer to page 3 of Micron’s technical note on thermal applications: TN-00-08. If functionality or operation is not a concern, refer to storage temperature specification limits on the part’s data sheet.

DDR SDRAM

Related Information

DDR Toolbox